8345 search results - page 1518 / 1669 » Design of Neuromorphic Hardwares |
184
click to vote
IPPS
2005
IEEE
16 years 1 days ago
2005
IEEE
Parallel random access memory, or PRAM, is a now venerable model of parallel computation that that still retains its usefulness for the design and analysis of parallel algorithms....
144
click to vote
ISCAS
2005
IEEE
16 years 1 days ago
2005
IEEE
— In a battery powered system, a primary design consideration is the battery lifetime. Profile of current drawn from a battery determines its lifetime. Recently in [4] dynamic v...
116
click to vote
ISCAS
2005
IEEE
16 years 1 days ago
2005
IEEE
—This paper describes a new low-power, area and pin efficient alternative to differential encoding for high performance chip-to-chip and backplane signaling. The technique, calle...
190
click to vote
ISCAS
2005
IEEE
16 years 1 days ago
2005
IEEE
— Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon...
156
click to vote
ISCAS
2005
IEEE
16 years 1 days ago
2005
IEEE
Abstract— We consider the problem of improving the performance of multiwavelets-based image coders through texture parametrization. Texture parametrization is designed to achieve...