Sciweavers

8345 search results - page 1513 / 1669
» Design of Neuromorphic Hardwares
Sort
View
ISLPED
2006
ACM
105views Hardware» more  ISLPED 2006»
16 years 13 days ago
Reducing power through compiler-directed barrier synchronization elimination
Interprocessor synchronization, while extremely important for ensuring execution correctness, can be very costly in terms of both power and performance overheads. Unfortunately, m...
Mahmut T. Kandemir, Seung Woo Son
ISLPED
2006
ACM
73views Hardware» more  ISLPED 2006»
16 years 13 days ago
Substituting associative load queue with simple hash tables in out-of-order microprocessors
Buffering more in-flight instructions in an out-of-order microprocessor is a straightforward and effective method to help tolerate the long latencies generally associated with ...
Alok Garg, Fernando Castro, Michael C. Huang, Dani...
IWCMC
2006
ACM
16 years 13 days ago
Radio propagation patterns in wireless sensor networks: new experimental results
Wireless sensors use low power radio transceivers due to the stringent constraints on battery capacity. As a result, radio transmission with wireless sensors is unreliable. Furthe...
Tereus Scott, Kui Wu, Daniel Hoffman
MM
2006
ACM
129views Multimedia» more  MM 2006»
16 years 13 days ago
GVU-PROCAMS: enabling novel projected interfaces
Front projection allows large displays to be deployed relatively easily. However, it is sometimes difficult to find a location to place a projector, especially for ad-hoc instal...
Jay Summet, Matthew Flagg, James M. Rehg, Gregory ...
SAC
2006
ACM
16 years 13 days ago
Building the functional performance model of a processor
In this paper, we present an efficient procedure for building a piecewise linear function approximation of the speed function of a processor with hierarchical memory structure. Th...
Alexey L. Lastovetsky, Ravi Reddy, Robert Higgins
« Prev « First page 1513 / 1669 Last » Next »