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DFT
2008
IEEE
106views VLSI» more  DFT 2008»
16 years 1 months ago
Built-In Proactive Tuning System for Circuit Aging Resilience
VLSI circuits in nanometer VLSI technology experience significant aging effects, which are embodied by performance degradation over operation time. Although this degradation can b...
Nimay Shah, Rupak Samanta, Ming Zhang, Jiang Hu, D...
DFT
2008
IEEE
117views VLSI» more  DFT 2008»
16 years 1 months ago
Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS
With each technology node shrink, a silicon chip becomes more susceptible to soft errors. The susceptibility further increases as the voltage is scaled down to save energy. Based ...
Vikas Chandra, Robert C. Aitken
DSN
2008
IEEE
16 years 1 months ago
A fault-tolerant directory-based cache coherence protocol for CMP architectures
Current technology trends of increased scale of integration are pushing CMOS technology into the deepsubmicron domain, enabling the creation of chips with a significantly greater...
Ricardo Fernández Pascual, José M. G...
GLOBECOM
2008
IEEE
16 years 1 months ago
Joint Channel and Mismatch Correction for OFDM Reception with Time-interleaved ADCs: Towards Mostly Digital MultiGigabit Transce
— Time-interleaved (TI) analog-to-digital converters (ADCs) are a promising architecture for realizing the highspeed ADCs required to implement “mostly digital” receivers for...
P. Sandeep, Upamanyu Madhow, Munkyo Seo, Mark J. W...
HPDC
2008
IEEE
16 years 1 months ago
The performance of bags-of-tasks in large-scale distributed systems
Ever more scientists are employing large-scale distributed systems such as grids for their computational work, instead of tightly coupled high-performance computing systems. Howev...
Alexandru Iosup, Omer Ozan Sonmez, Shanny Anoep, D...
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