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» Design of Neuromorphic Hardwares
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DATE
2010
IEEE
193views Hardware» more  DATE 2010»
15 years 11 months ago
Coordinated resource optimization in behavioral synthesis
Abstract—Reducing resource usage is one of the most important optimization objectives in behavioral synthesis due to its direct impact on power, performance and cost. The datapat...
Jason Cong, Bin Liu, Junjuan Xu
ISCA
2010
IEEE
210views Hardware» more  ISCA 2010»
15 years 11 months ago
An intra-chip free-space optical interconnect
Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless s...
Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun ...
ISCA
2010
IEEE
340views Hardware» more  ISCA 2010»
15 years 11 months ago
Necromancer: enhancing system throughput by animating dead cores
Aggressive technology scaling into the nanometer regime has led to a host of reliability challenges in the last several years. Unlike onchip caches, which can be efficiently prot...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
ASAP
2002
IEEE
170views Hardware» more  ASAP 2002»
15 years 11 months ago
Reviewing 4-to-2 Adders for Multi-Operand Addition
Recently there has been quite a number of papers discussing the use of redundant 4-to-2 adders for the accumulation of partial products in multipliers, claiming one type to be sup...
Peter Kornerup
CLUSTER
2002
IEEE
15 years 11 months ago
Scalable Resource Management in High Performance Computers
Clusters of workstations have emerged as an important platform for building cost-effective, scalable, and highlyavailable computers. Although many hardware solutions are available...
Eitan Frachtenberg, Fabrizio Petrini, Juan Fern&aa...
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