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» Design of Neuromorphic Hardwares
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ISCA
2005
IEEE
119views Hardware» more  ISCA 2005»
16 years 6 days ago
Rescue: A Microarchitecture for Testability and Defect Tolerance
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
Ethan Schuchman, T. N. Vijaykumar
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
16 years 6 days ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
ISCA
2005
IEEE
105views Hardware» more  ISCA 2005»
16 years 6 days ago
Exploiting Structural Duplication for Lifetime Reliability Enhancement
Increased power densities (and resultant temperatures) and other effects of device scaling are predicted to cause significant lifetime reliability problems in the near future. In...
Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, J...
ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
16 years 6 days ago
A High Throughput String Matching Architecture for Intrusion Detection and Prevention
Network Intrusion Detection and Prevention Systems have emerged as one of the most effective ways of providing security to those connected to the network, and at the heart of alm...
Lin Tan, Timothy Sherwood
MICRO
2005
IEEE
113views Hardware» more  MICRO 2005»
16 years 6 days ago
Thermal Management of On-Chip Caches Through Power Density Minimization
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I....
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