8345 search results - page 1443 / 1669 » Design of Neuromorphic Hardwares |
197
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IEEEPACT
2006
IEEE
16 years 20 days ago
2006
IEEE
As chip multiprocessors (CMPs) become increasingly mainstream, architects have likewise become more interested in how best to share a cache hierarchy among multiple simultaneous t...
160
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ISCA
2006
IEEE
16 years 19 days ago
2006
IEEE
The key to high performance in Simultaneous Multithreaded (SMT) processors lies in optimizing the distribution of shared resources to active threads. Existing resource distributio...
178
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ISCA
2006
IEEE
16 years 19 days ago
2006
IEEE
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
153
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ISQED
2006
IEEE
16 years 19 days ago
2006
IEEE
It is well known that fill insertion adversely affects total and coupling capacitance of interconnects. While grounded fill can be extracted by full-chip extractors, floating ...
164
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MICRO
2006
IEEE
16 years 19 days ago
2006
IEEE
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...