8345 search results - page 1441 / 1669 » Design of Neuromorphic Hardwares |
172
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ISQED
2007
IEEE
16 years 27 days ago
2007
IEEE
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
166
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ISQED
2007
IEEE
16 years 27 days ago
2007
IEEE
In this paper, we address the interconnect-driven floorplanning problem that integrates OPC-friendly bus assignment with floorplanning. Buses consist of a number of horizontal/v...
193
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MICRO
2007
IEEE
16 years 27 days ago
2007
IEEE
The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a singl...
170
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MICRO
2007
IEEE
16 years 27 days ago
2007
IEEE
Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower sup...
180
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MICRO
2007
IEEE
16 years 27 days ago
2007
IEEE
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...