8345 search results - page 1435 / 1669 » Design of Neuromorphic Hardwares |
219
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SASP
2009
IEEE
16 years 1 months ago
2009
IEEE
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
173
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ISCA
2009
IEEE
16 years 1 months ago
2009
IEEE
Data prefetching has long been an important technique to amortize the effects of the memory wall, and is likely to remain so in the current era of multi-core systems. Most prefetc...
200
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ISCA
2009
IEEE
16 years 1 months ago
2009
IEEE
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. A...
170
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MICRO
2009
IEEE
16 years 1 months ago
2009
IEEE
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
197
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MICRO
2009
IEEE
16 years 1 months ago
2009
IEEE
Cache blocks often exhibit a small number of uses during their life time in the last-level cache. Past research has exploited this property in two different ways. First, replacem...