Sciweavers

8345 search results - page 1418 / 1669
» Design of Neuromorphic Hardwares
Sort
View
AICCSA
2006
IEEE
137views Hardware» more  AICCSA 2006»
16 years 22 days ago
Modeling Redundancy: Quantitative and Qualitative Models
Redundancy is a system property that generally refers to duplication of state information or system function. While redundancy is usually investigated in the context of fault tole...
Ali Mili, Lan Wu, Frederick T. Sheldon, Mark Shere...
CODES
2006
IEEE
16 years 22 days ago
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
Martijn Coenen, Srinivasan Murali, Andrei Radulesc...
CODES
2006
IEEE
16 years 22 days ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt
FCCM
2006
IEEE
131views VLSI» more  FCCM 2006»
16 years 22 days ago
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
Nachiket Kapre, Nikil Mehta, Michael DeLorimier, R...
ASPLOS
2006
ACM
16 years 19 days ago
Type inference for unboxed types and first class mutability
Systems programs rely on fine-grain control of data representation and use of state to achieve performance, conformance to hardware specification, and temporal predictability. T...
Swaroop Sridhar, Jonathan S. Shapiro
« Prev « First page 1418 / 1669 Last » Next »