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» Design of Neuromorphic Hardwares
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CODES
2007
IEEE
16 years 1 months ago
Predator: a predictable SDRAM memory controller
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
Benny Akesson, Kees Goossens, Markus Ringhofer
CODES
2007
IEEE
16 years 1 months ago
Event-based re-training of statistical contention models for heterogeneous multiprocessors
Embedded single-chip heterogeneous multiprocessor (SCHM) systems experience frequent system events such as task preemption, power-saving voltage/frequency scaling, or arrival of n...
Alex Bobrek, JoAnn M. Paul, Donald E. Thomas
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CODES
2007
IEEE
16 years 1 months ago
Performance modeling for early analysis of multi-core systems
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittman...
ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
16 years 20 days ago
Crosstalk analysis using reconvergence correlation
Abstract— In the UDSM era, crosstalk is an area of considerable concern for designers, as it can have a considerable impact on the yield, both in terms of functionality and opera...
Sachin Shrivastava, Rajendra Pratap, Harindranath ...
ISLPED
2006
ACM
117views Hardware» more  ISLPED 2006»
16 years 19 days ago
Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)
As transistors continue to scale down into the nanometer regime, device leakage currents are becoming the dominant cause of power dissipation in nanometer caches, making it essent...
Samuel Rodríguez, Bruce L. Jacob
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