8345 search results - page 1395 / 1669 » Design of Neuromorphic Hardwares |
153
Voted
ISCA
2003
IEEE
15 years 12 months ago
2003
IEEE
Many future shared-memory multiprocessor servers will both target commercial workloads and use highly-integrated “glueless” designs. Implementing low-latency cache coherence i...
176
Voted
MICRO
2003
IEEE
15 years 12 months ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
157
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MICRO
2003
IEEE
15 years 12 months ago
2003
IEEE
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
165
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ISLPED
2003
ACM
15 years 12 months ago
2003
ACM
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
158
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ISPD
2003
ACM
15 years 12 months ago
2003
ACM
: Recent years have seen significant research in finding closed form expressions for the delay of an RC circuit that improves upon the Elmore delay model. However, several of these...