Sciweavers

8345 search results - page 1394 / 1669
» Design of Neuromorphic Hardwares
Sort
View
ISPD
2004
ACM
189views Hardware» more  ISPD 2004»
16 years 4 days ago
Almost optimum placement legalization by minimum cost flow and dynamic programming
VLSI placement tools usually work in two steps: First, the cells that have to be placed are roughly spread out over the chip area ignoring disjointness (global placement). Then, i...
Ulrich Brenner, Anna Pauli, Jens Vygen
ISPD
2004
ACM
134views Hardware» more  ISPD 2004»
16 years 4 days ago
Performance-driven register insertion in placement
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
Dennis K. Y. Tong, Evangeline F. Y. Young
PACS
2004
Springer
115views Hardware» more  PACS 2004»
16 years 1 days ago
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, ...
DATE
2003
IEEE
101views Hardware» more  DATE 2003»
15 years 12 months ago
Energy Estimation for Extensible Processors
This paper presents an efficient methodology for estimating the energy consumption of application programs running on extensible processors. Extensible processors, which are incr...
Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj...
GLVLSI
2003
IEEE
180views VLSI» more  GLVLSI 2003»
15 years 12 months ago
3D direct vertical interconnect microprocessors test vehicle
The current trends in high performance integrated circuits are towards faster and more powerful circuits in the giga-hertz range and even further. As the more complex Integrated C...
John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan...
« Prev « First page 1394 / 1669 Last » Next »