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» Design of Neuromorphic Hardwares
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ISLPED
2003
ACM
142views Hardware» more  ISLPED 2003»
15 years 12 months ago
Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization
We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous a...
David Nguyen, Abhijit Davare, Michael Orshansky, D...
ISLPED
2003
ACM
94views Hardware» more  ISLPED 2003»
15 years 12 months ago
A 0.75-mW analog processor IC for wireless biosignal monitor
This work presents a single-channel analog processor IC for the wireless biosignal monitor. This chip occupies a small die area of 0.52 mm2 and has a low power consumption of 0.75...
Chih-Jen Yen, Mely Chen Chi, Wen-Yaw Chung, Shing-...
FPGA
2003
ACM
154views FPGA» more  FPGA 2003»
15 years 12 months ago
Parallel placement for field-programmable gate arrays
Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmable gate arrays (FPGAs). In this paper, we ...
Pak K. Chan, Martine D. F. Schlag
GLVLSI
2002
IEEE
95views VLSI» more  GLVLSI 2002»
15 years 11 months ago
Term ordering problem on MDG
As an efficient representation of Extended Finite State Machines, Multiway Decision Graphs (MDG) are suitable for automatic hardware verification of Register Transfer Level (RTL) ...
Yi Feng, Eduard Cerny
GLVLSI
2002
IEEE
109views VLSI» more  GLVLSI 2002»
15 years 11 months ago
Minimizing resources in a repeating schedule for a split-node data-flow graph
Many computation-intensive or recursive applications commonly found in digital signal processing and image processing applications can be represented by data-flow graphs (DFGs). ...
Timothy W. O'Neil, Edwin Hsing-Mean Sha
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