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IEEEPACT
2006
IEEE
16 years 24 days ago
Core architecture optimization for heterogeneous chip multiprocessors
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi
IPPS
2006
IEEE
16 years 24 days ago
Towards building a highly-available cluster based model for high performance computing
In recent years, we have witnessed a growing interest in high performance computing (HPC) using a cluster of workstations. However, many challenges remain to be resolved before th...
Azzedine Boukerche, Raed Al-Shaikh, Mirela Sechi M...
IPPS
2006
IEEE
16 years 24 days ago
Selection of instruction set extensions for an FPGA embedded processor core
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The i...
Brian F. Veale, John K. Antonio, Monte P. Tull, S....
IROS
2006
IEEE
140views Robotics» more  IROS 2006»
16 years 24 days ago
Developing a non-intrusive biometric environment
— The development of large scale biometric systems requires experiments to be performed on large amounts of data. Existing capture systems are designed for fixed experiments and...
Lee Middleton, David K. Wagg, Alex I. Bazin, John ...
ISCAS
2006
IEEE
98views Hardware» more  ISCAS 2006»
16 years 24 days ago
Second order dynamic element matching technique for low oversampling delta sigma ADC
There has been an increased interest in design of that it can give better performance, if a modified noise broadband (data rate >IMSPS) delta sigma ADCs with over- transfer func...
A. K. Gupta, E. Sanchez-Sinencio, S. Karthikeyan, ...
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