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FMCAD
2007
Springer
16 years 28 days ago
Formal Verification of Partial Good Self-Test Fencing Structures
— The concept of applying partial fencing to logic built-in self test (LBIST) hardware structures for the purpose of using partially good chips is well known in the chip design i...
Adrian E. Seigler, Gary A. Van Huben, Hari Mony
FPGA
2007
ACM
153views FPGA» more  FPGA 2007»
16 years 28 days ago
GlitchLess: an active glitch minimization technique for FPGAs
This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...
FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
16 years 28 days ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier
GPCE
2007
Springer
16 years 28 days ago
42: programmable models of computation for a component-based approach to heterogeneous embedded systems
Every notion of a component for the development of embedded systems has to take heterogeneity into account: components may be hardware or software or OS, synchronous or asynchrono...
Florence Maraninchi, Tayeb Bouhadiba
CLUSTER
2006
IEEE
16 years 25 days ago
Cluster-based IP Router: Implementation and Evaluation
IP routers are now increasingly expected to do more than just traditional packet forwarding – they must be extensible as well as scalable. It is a challenge to design a router a...
Qinghua Ye, Mike H. MacGregor
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