8345 search results - page 1348 / 1669 » Design of Neuromorphic Hardwares |
141
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ISCAS
2007
IEEE
16 years 1 months ago
2007
IEEE
—This paper presents a DAC architecture built on parallel current-steering sub-DAC entities. Two main novelties are explored: flexibility and smartness. Firstly, a number of avai...
168
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ISCAS
2007
IEEE
16 years 1 months ago
2007
IEEE
—Systems on Chip (SoCs) congregate multiple modules and advanced interconnection schemes, such as networks on chip (NoCs). One relevant problem in SoC design is module mapping on...
136
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ISCAS
2007
IEEE
16 years 1 months ago
2007
IEEE
— In this paper we will present the architecture of the planar biped robot “RunBot”. It has been developed on the basis of three hierarchical levels: Biomechanical, Local and...
174
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ISCAS
2007
IEEE
16 years 1 months ago
2007
IEEE
—The coding performance can be further improved when the hierarchical B-picture coding is introduced into H.264/AVC. However, the existing rate control schemes can NOT work effic...
205
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ISVLSI
2007
IEEE
16 years 1 months ago
2007
IEEE
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...