8345 search results - page 1336 / 1669 » Design of Neuromorphic Hardwares |
207
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CODES
2003
IEEE
16 years 2 days ago
2003
IEEE
In the Sesame framework, we develop a modeling and simulation environment for the efficient design space exploration of heterogeneous embedded systems. Since Sesame recognizes se...
183
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FPGA
2003
ACM
16 years 7 hour ago
2003
ACM
This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contri...
190
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CODES
1999
IEEE
15 years 11 months ago
1999
IEEE
o much higher levels of abstraction than today's design practices, which are usually at the level of synthesizable RTL for custom hardware or Instruction Set Simulator (ISS) f...
217
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GLVLSI
2009
IEEE
2009
IEEE
Physical unclonable function and true random number generator: a compact and scalable implementation
15 years 10 months ago
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signat...
233
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DELTA
2006
IEEE
15 years 10 months ago
2006
IEEE
This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be i...