8345 search results - page 1326 / 1669 » Design of Neuromorphic Hardwares |
171
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ISCA
2007
IEEE
16 years 1 months ago
2007
IEEE
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
188
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ISCA
2007
IEEE
16 years 1 months ago
2007
IEEE
Hardware transactional memory has great potential to simplify the creation of correct and efficient multithreaded programs, allowing programmers to exploit more effectively the s...
188
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MICRO
2007
IEEE
16 years 1 months ago
2007
IEEE
Transactional Memory (TM) systems must track the read and write sets—items read and written during a transaction—to detect conflicts among concurrent transactions. Several TM...
213
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LCTRTS
2007
Springer
16 years 28 days ago
2007
Springer
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
193
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SAMOS
2007
Springer
16 years 28 days ago
2007
Springer
— General purpose architectures are designed to offer average high performance regardless of the particular application that is being run. Performance and power inefficiencies a...