Sciweavers

8345 search results - page 1299 / 1669
» Design of Neuromorphic Hardwares
Sort
View
ISHPC
2003
Springer
16 years 1 days ago
A Simple Low-Energy Instruction Wakeup Mechanism
Instruction issue consumes a large amount of energy in out of order processors, largely in the wakeup logic. Proposed solutions to the problem require prediction or additional hard...
Marco A. Ramírez, Adrián Cristal, Al...
ASAP
2009
IEEE
131views Hardware» more  ASAP 2009»
15 years 12 months ago
Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system
This paper presents a new constraint-driven method for computational pattern selection, mapping and application scheduling using reconfigurable processor extensions. The presente...
Kevin Martin, Christophe Wolinski, Krzysztof Kuchc...
167
Voted
ISMVL
2010
IEEE
191views Hardware» more  ISMVL 2010»
15 years 12 months ago
Toffoli Gate Implementation Using the Billiard Ball Model
— In this paper we review the Billiard Ball Model (BBM) introduced by Toffoli and Fredkin. The analysis of a previous approach to design reversible networks based on BBM it shown...
Hadi Hosseini, Gerhard W. Dueck
AUIC
2002
IEEE
15 years 11 months ago
Building Multi-Device, Component-based, Thin-client Groupware: Issues and Experiences
The use of groupware, or collaborative work-supporting technologies, has become wide-spread, but many existing groupware systems are too difficult to integrate with domain-specifi...
John C. Grundy, Xing Wang, John G. Hosking
CODES
2002
IEEE
15 years 11 months ago
Worst-case performance analysis of parallel, communicating software processes
In this paper we present a method to perform static timing analysis of SystemC models, that describe parallel, communicating software processes.The paper combines a worstcase exec...
Axel Siebenborn, Oliver Bringmann, Wolfgang Rosens...
« Prev « First page 1299 / 1669 Last » Next »