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» Design of Neuromorphic Hardwares
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179
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IOLTS
2003
IEEE
138views Hardware» more  IOLTS 2003»
16 years 4 days ago
An Analog Checker With Input-Relative Tolerance for Duplicate Signals
We discuss the design of a novel analog checker that monitors two duplicate signals and provides a digital error indication when their absolute difference is unacceptably large. Th...
Haralampos-G. D. Stratigopoulos, Yiorgos Makris
IPPS
2003
IEEE
16 years 4 days ago
Remote Model Reduction of Very Large Linear Systems
We describe a prototype Web service for model reduction of very large-scale linear systems. Specifically, a userfriendly interface is designed so that model reduction can be easi...
Peter Benner, Rafael Mayo, Enrique S. Quintana-Ort...
ISCAS
2003
IEEE
78views Hardware» more  ISCAS 2003»
16 years 4 days ago
SLAP: a system for the detection and correction of pronunciation for second language acquisition
We describe a system for the training of Second Language Acquisition Pronunciation (SLAP) for nonnative speakers. This speech recognition-based system is designed to mimic the val...
Lingyun Gu, John G. Harris
ISCAS
2003
IEEE
126views Hardware» more  ISCAS 2003»
16 years 4 days ago
Bit rate optimized time-domain equalizers for DMT systems
The discrete multitone (DMT)transceivers have enjoyed great success in high speed data transmission. It is known that when the cyclicprefix is no shorterthan the channel impulse r...
Chun-Yang Chen, See-May Phoong
175
Voted
ISCAS
2003
IEEE
77views Hardware» more  ISCAS 2003»
16 years 4 days ago
Inductive interconnect width optimization for low power
The width of an interconnect line a ects the total power consumed by a circuit. A tradeo exists, however, between the dynamic power and the short-circuit power in determining the ...
Magdy A. El-Moursy, Eby G. Friedman
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