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201
Voted
ISCAS
2005
IEEE
16 years 14 days ago
2005
IEEE
— This paper is devoted to receiver design in a Chaotic Direct-Sequence Spread Spectrum (CD3S) digital communication system. The demodulation is achieved through chaos synchroniz...
186
Voted
MSS
2005
IEEE
16 years 13 days ago
2005
IEEE
To meet enterprise and grand challenge-scale performance and interoperability requirements, a group of engineers—initially ad-hoc but now integrated into the IETF—is designing...
171
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MSS
2005
IEEE
16 years 13 days ago
2005
IEEE
Recent advances in large-capacity, low-cost storage devices have led to active research in design of large-scale storage systems built from commodity devices for supercomputing ap...
144
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VTS
2005
IEEE
16 years 13 days ago
2005
IEEE
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
170
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WORDS
2005
IEEE
16 years 13 days ago
2005
IEEE
Reliable program Worst-Case Execution Time (WCET) estimates are a key component when designing and verifying real-time systems. One way to derive such estimates is by static WCET ...