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ISCAS
2005
IEEE
138views Hardware» more  ISCAS 2005»
16 years 14 days ago
A low spur fractional-N frequency synthesizer architecture
— A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loo...
Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moo...
ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
16 years 14 days ago
A high performance distributed-parallel-processor architecture for 3D IIR digital filters
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
Arjuna Madanayake, Leonard T. Bruton
ISCAS
2005
IEEE
154views Hardware» more  ISCAS 2005»
16 years 14 days ago
Boost-buck inverter variable structure control for grid-connected photovoltaic systems
—The present work describes the analysis, modeling and control of a transformerless Boost-Buck power inverter used as a DC-AC power conditioning stage for grid-connected photovol...
Carlos Meza, Domingo Biel, Luis Martinez-Salamero,...
ISCAS
2005
IEEE
140views Hardware» more  ISCAS 2005»
16 years 14 days ago
Low energy asynchronous architectures
: Asynchronous circuits are often presented as a means of achieving low power operation. We investigate their suitability for low-energy applications, where long battery life and d...
Ilya Obridko, Ran Ginosar
ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
16 years 14 days ago
A distributed FIFO scheme for on chip communication
— Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because of disturbances that result from parasiti...
Ray Robert Rydberg III, Jabulani Nyathi, Jos&eacut...
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