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160
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ASPDAC
2006
ACM
16 years 26 days ago
2006
ACM
- Traditionally, minimum possible area of a VLSI layout is considered the best for delay and power minimization due to decreased interconnect capacitance. This paper shows however ...
160
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ASPDAC
2006
ACM
16 years 26 days ago
2006
ACM
- Reducing the yield loss due to via failure is one of the important problems in design for manufacturability. A well known and highly recommended method to improve via yield/relia...
147
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ASPDAC
2006
ACM
16 years 26 days ago
2006
ACM
— As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an efficien...
189
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ASPDAC
2006
ACM
16 years 26 days ago
2006
ACM
– We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and cro...
155
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ASPDAC
2006
ACM
16 years 26 days ago
2006
ACM
- With the increasing demand for SoCs to include rich functionality, SoCs are being designed with hundreds of small memories with different sizes and frequencies. If memory BIST lo...