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ISCAS
1994
IEEE
138views Hardware» more  ISCAS 1994»
15 years 10 months ago
High-Throughput Data Compressor Designs Using Content Addressable Memory
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
Ren-Yang Yang, Chen-Yi Lee
DATE
2009
IEEE
115views Hardware» more  DATE 2009»
15 years 10 months ago
Customizing IP cores for system-on-chip designs using extensive external don't-cares
Traditional digital circuit synthesis flows start from an HDL behavioral definition and assume that circuit functions are almost completely defined, making don't-care conditio...
Kai-Hui Chang, Valeria Bertacco, Igor L. Markov
HAPTICS
2009
IEEE
15 years 4 months ago
A 2D haptic glyph method for tactile arrays : Design and evaluation
We present a new framework for information cue rendering on 2D vibrotactile arrays, and we describe an experiment that investigated the feasibility of our approach. The methods ar...
Christoph W. Borst, Vijay B. Baiyya
ICIP
2007
IEEE
16 years 8 months ago
Analysis and Integrated Architecture Design for Overlap Smooth and in-Loop Deblocking Filter in VC-1
Unlike familiar macroblock-based in-loop deblocking filter in H.264, the filters of VC-1 perform all horizontal edges (for in-loop deblocking filtering) or vertical edges (for ove...
Yen-Lin Lee, Truong Nguyen
ISORC
2000
IEEE
15 years 11 months ago
Hybrid Sequence Charts
We introduce Hybrid Sequence Charts (HySCs) as a visual description technique for communication in hybrid system models. To that end, we adapt a subset of the well-known MSC synta...
Radu Grosu, Ingolf Krüger, Thomas Stauner