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DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
16 years 11 days ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
MTDT
2003
IEEE
164views Hardware» more  MTDT 2003»
15 years 11 months ago
Applying Defect-Based Test to Embedded Memories in a COT Model
ct Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defe...
Robert C. Aitken
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
16 years 11 days ago
Engineering trust with semantic guardians
The ability to guarantee the functional correctness of digital integrated circuits and, in particular, complex microprocessors, is a key task in the production of secure and trust...
Ilya Wagner, Valeria Bertacco
EH
2003
IEEE
136views Hardware» more  EH 2003»
15 years 11 months ago
Experimental Results in Evolutionary Fault-Recovery for Field Programmable
This paper presents experimental results of fast intrinsic evolutionary design and evolutionary fault recovery of a 4-bit Digital to Analog Converter (DAC) using the JPL stand-alo...
Ricardo Salem Zebulum, Didier Keymeulen, Vu Duong,...
FPGA
2005
ACM
195views FPGA» more  FPGA 2005»
15 years 11 months ago
Sparse Matrix-Vector multiplication on FPGAs
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
Ling Zhuo, Viktor K. Prasanna