305 search results - page 48 / 61 » Design of Digital Circuits on the Basis of Hardware Template... |
150
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ISQED
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
139
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ICCAD
2008
IEEE
16 years 2 months ago
2008
IEEE
– Due to reduction in device feature size and supply voltage, the sensitivity of digital systems to transient faults is increasing dramatically. As technology scales further, the...
132
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ACSD
2010
IEEE
15 years 4 months ago
2010
IEEE
Abstract--Clock gating and operand isolation are two techniques to reduce the power consumption in state-of-the-art hardware designs. Both approaches basically follow a two-step pr...
141
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ICCAD
1998
IEEE
15 years 10 months ago
1998
IEEE
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...
194
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GECCO
2008
Springer
15 years 7 months ago
2008
Springer
The choice of an appropriate hardware representation model is key to successful evolution of digital circuits. One of the most popular models is cartesian genetic programming, whi...