305 search results - page 31 / 61 » Design of Digital Circuits on the Basis of Hardware Template... |
170
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CAI
2004
Springer
15 years 6 months ago
2004
Springer
A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evo...
151
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DATE
2003
IEEE
15 years 11 months ago
2003
IEEE
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...
119
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ISCAS
2008
IEEE
16 years 15 days ago
2008
IEEE
— This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay...
133
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ICCAD
2003
IEEE
16 years 3 months ago
2003
IEEE
We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle ana...
153
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ICCS
2007
Springer
16 years 7 days ago
2007
Springer
This paper describes a signal recognition system that is jointly optimized from mathematical representation, algorithm design and final implementation. The goal is to exploit sign...