305 search results - page 30 / 61 » Design of Digital Circuits on the Basis of Hardware Template... |
152
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ISLPED
2009
ACM
15 years 10 months ago
2009
ACM
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
171
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ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...
172
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ISQED
2008
IEEE
16 years 15 days ago
2008
IEEE
Large-scale process fluctuations (particularly random device mismatches) at nanoscale technologies bring about highdimensional strongly nonlinear performance variations that canno...
153
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ICCAD
2007
IEEE
16 years 12 days ago
2007
IEEE
—In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamic...
128
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DATE
2000
IEEE
15 years 10 months ago
2000
IEEE
An objective of DSP testing should be to ensure that any errors due to missed faults are infrequent compared to a circuit’s intrinsic errors, such as overflow. A method is prop...