305 search results - page 28 / 61 » Design of Digital Circuits on the Basis of Hardware Template... |
173
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ISCAS
2006
IEEE
16 years 3 days ago
2006
IEEE
—This paper introduces a technique to measure and adjust the relative phase of on-chip high speed digital signals using a random sampling technique of inferential statistics. The...
138
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ISCAS
2007
IEEE
16 years 11 days ago
2007
IEEE
— Low-power consumption has become a highly important concern for synchronous standard-cell design, and consequently mandates the use of low-power design methodologies and techni...
153
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EVOW
1999
Springer
15 years 10 months ago
1999
Springer
The traditional paradigm for digital filter design is based on the concept of a linear difference equation with the output response being a weighted sum of signal samples with usua...
198
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ISQED
2011
IEEE
14 years 9 months ago
2011
IEEE
—Design optimization methodologies for AMS-SoCs with analog, digital, and mixed-signal portions have not received significant attention, due to their high complexity. In mixed-s...
237
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FPGA
2003
ACM
15 years 11 months ago
2003
ACM
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...