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VTS
2003
IEEE
81views Hardware» more  VTS 2003»
15 years 11 months ago
Test Resource Partitioning and Optimization for SOC Designs
1 We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the ai...
Erik Larsson, Hideo Fujiwara
TC
2010
15 years 1 months ago
FPGA Designs with Optimized Logarithmic Arithmetic
Using a general polynomial approximation approach, we present an arithmetic library generator for the logarithmic number system (LNS). The generator produces optimized LNS arithmet...
Haohuan Fu, Oskar Mencer, Wayne Luk
TSP
2010
15 years 1 months ago
Optimized analog flat filter design
This paper proposes a systematic approach for the optimized design of analog filters, which includes all well-known classical analog filters as a special case. All specifications i...
Hung Gia Hoang, Hoang Duong Tuan, Truong Q. Nguyen
ASPDAC
2008
ACM
101views Hardware» more  ASPDAC 2008»
15 years 8 months ago
Interconnect modeling for improved system-level design optimization
Accurate modeling of delay, power, and area of interconnections early in the design phase is crucial for effective system-level optimization. Models presently used in system-level...
Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Ale...
DATE
2010
IEEE
160views Hardware» more  DATE 2010»
15 years 11 months ago
Soft error-aware design optimization of low power and time-constrained embedded systems
— In this paper, we examine the impact of application task mapping on the reliability of MPSoC in the presence of single-event upsets (SEUs). We propose a novel soft erroraware d...
Rishad A. Shafik, Bashir M. Al-Hashimi, Krishnendu...