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DATE
2000
IEEE
142views Hardware» more  DATE 2000»
15 years 11 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
ISPD
2004
ACM
150views Hardware» more  ISPD 2004»
16 years 9 days ago
Topology optimization of structured power/ground networks
This paper presents an efficient method for optimizing the design of power/ground (P/G) networks by using locally regular, globally irregular grids. The procedure divides the pow...
Jaskirat Singh, Sachin S. Sapatnekar
LCN
2002
IEEE
15 years 11 months ago
Optimization of AP Placement and Channel Assignment in Wireless LANs
—The design of a wireless local area network (WLAN) has an important issue of determining the optimal placement of access points (APs) and assignment of channels to them. WLAN se...
Youngseok Lee, Kyoungae Kim, Yanghee Choi
ASPDAC
2004
ACM
79views Hardware» more  ASPDAC 2004»
15 years 10 months ago
NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO
Abstract--A parasitic-aware RF synthesis tool based on a nondominated sorting genetic algorithm (NSGA) is introduced. The NSGA-based optimizer casts the design problem as a multi-o...
Min Chu, David J. Allstot, Jeffrey M. Huard, Kim Y...
ASPDAC
2008
ACM
145views Hardware» more  ASPDAC 2008»
15 years 9 months ago
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches
- We present a topology synthesis method for high performance System-on-Chip (SoC) design. Our method provides an optimal topology of on-chip communication network for the given ba...
Minje Jun, Sungjoo Yoo, Eui-Young Chung