With the fast growing size and complexity of core network, the hash based data structure of current AS_PATH implementation in BGP is facing challenges in performance, mainly caused...
The design of the Eiffel language makes it possible to perform global optimizations on Eiffel programs. In this paper, we describe some of the techniques we used in SmallEiffel, T...
This paper presents the design of an ASIC intended for optimal edge detection of blurred and noisy 2-D images. The chip has a parallel and pipelined architecture which processes a...
This paper presents a tactile transducer device that is optimized from biomechanical data and has a compact, yet modular design. The tactile transducer comprises a 6 × 10 piezo b...
Starting from the 90nm technology node, process induced stress has played a key role in the design of highperformance devices. The emergence of source/drain silicon germanium (S/D ...