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DATE
2005
IEEE
115views Hardware» more  DATE 2005»
16 years 12 days ago
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
Rui Rodrigues, João M. P. Cardoso
GECCO
2004
Springer
120views Optimization» more  GECCO 2004»
16 years 5 days ago
Comparison of Selection Strategies for Evolutionary Quantum Circuit Design
Evolution of quantum circuits faces two major challenges: complex and huge search spaces and the high costs of simulating quantum circuits on conventional computers. In this paper ...
André Leier, Wolfgang Banzhaf
177
Voted
RTSS
2003
IEEE
16 years 2 days ago
A Hybrid Control Design for QoS Management
In this paper we present an approach for QoS management that can be applied to a general class of real-time distributed computation systems. In the proposed approach a switching h...
Sherif Abdelwahed, Sandeep Neema, Joseph P. Loyall...
DATE
2002
IEEE
158views Hardware» more  DATE 2002»
15 years 11 months ago
Congestion Estimation with Buffer Planning in Floorplan Design
In this paper, we study and implement a routabilitydriven floorplanner with buffer block planning. It evaluates the routability of a floorplan by computing the probability that ...
Wai-Chiu Wong, Chiu-Wing Sham, Evangeline F. Y. Yo...
PARCO
2003
15 years 8 months ago
SIMD design to solve partial differential equations
The relation between autonomous and communication phases determines the throughput of parallel structured information processing systems. Such a relation depends on the algorithm w...
R. W. Schulze