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ASPDAC
2006
ACM
105views Hardware» more  ASPDAC 2006»
16 years 21 days ago
Speed binning aware design methodology to improve profit under parameter variations
—Designing high-performance systems with high yield under parameter variations has raised serious design challenges in nanometer technologies. In this paper, we propose a profit-...
Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saib...
FCCM
1998
IEEE
113views VLSI» more  FCCM 1998»
15 years 11 months ago
PAM-Blox: High Performance FPGA Design for Adaptive Computing
PAM-Blox are object-oriented circuit generators on top of the PCI Pamette design environment, PamDC. High- performance FPGA design for adaptive computing is simplified by using a ...
Oskar Mencer, Martin Morf, Michael J. Flynn
ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
16 years 24 days ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
DAC
1997
ACM
15 years 11 months ago
Structured Design of Microelectromechanical Systems
In order to efficiently design complex microelectromechanical systems (MEMS) having large numbers of multi-domain components, a hierarchically structured design approach that is ...
Tamal Mukherjee, Gary K. Fedder
FPGA
2008
ACM
163views FPGA» more  FPGA 2008»
15 years 8 months ago
TORCH: a design tool for routing channel segmentation in FPGAs
A design tool for routing channel segmentation in islandstyle FPGAs is presented. Given the FPGA architecture parameters and a set of benchmark designs, the tool optimizes routing...
Mingjie Lin, Abbas El Gamal