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ICCAD
1998
IEEE
95views Hardware» more  ICCAD 1998»
15 years 11 months ago
Efficient analog circuit synthesis with simultaneous yield and robustness optimization
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
Geert Debyser, Georges G. E. Gielen
EURODAC
1995
IEEE
101views VHDL» more  EURODAC 1995»
15 years 10 months ago
Exploiting power-up delay for sequential optimization
Recent work has identified the notion of safe replacement for sequential synchronousdesigns that may not have reset hardware or even explicitly known initial states. Safe replace...
Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K....
AHS
2007
IEEE
262views Hardware» more  AHS 2007»
15 years 8 months ago
A Reed-Solomon Algorithm for FPGA Area Optimization in Space Applications
This work describes an algebraic based design strategy targeting area optimization in reconfigurable computer technology (FPGA). Area optimization is a major issue as smaller comp...
Gabriel Marchesan Almeida, Eduardo Augusto Bezerra...
ICCAD
2007
IEEE
98views Hardware» more  ICCAD 2007»
16 years 3 months ago
Device-circuit co-optimization for mixed-mode circuit design via geometric programming
Modern processing technologies offer a number of types of devices such as high-VT , low-VT , thick-oxide, etc. in addition to the nominal transistor in order to meet system perfor...
Jintae Kim, Ritesh Jhaveri, Jason Woo, Chih-Kong K...
DAC
2000
ACM
16 years 7 months ago
Code compression for low power embedded system design
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
Haris Lekatsas, Jörg Henkel, Wayne Wolf