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CODES
2008
IEEE
16 years 1 months ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava
ICASSP
2008
IEEE
16 years 1 months ago
Systematic generation of FPGA-based FFT implementations
In this paper, we propose a systemic approach for synthesizing field-programmable gate array (FPGA) implementations of fast Fourier transform (FFT) computations. Our approach cons...
Hojin Kee, Newton Petersen, Jacob Kornerup, Shuvra...
INFOCOM
2008
IEEE
16 years 1 months ago
Fast and Distributed Computation of Schedules in Wireless Networks
—In a wireless network with node exclusive spectrum sharing, two popular schedules are maximum weight matching (MWM) schedule and maximum size matching (MSM) schedule. The former...
Supratim Deb, Karan Mangla, K. V. M. Naidu
CODES
2007
IEEE
16 years 1 months ago
Reliable multiprocessor system-on-chip synthesis
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, L...
CODES
2007
IEEE
16 years 1 months ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
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