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ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
16 years 13 days ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
TIP
2008
141views more  TIP 2008»
15 years 6 months ago
Spatio-Spectral Color Filter Array Design for Optimal Image Recovery
Abstract--In digital imaging applications, data are typically obtained via a spatial subsampling procedure implemented as a color filter array--a physical construction whereby only...
Keigo Hirakawa, Patrick J. Wolfe
ICDCS
2007
IEEE
16 years 22 days ago
Protocol Design and Optimization for Delay/Fault-Tolerant Mobile Sensor Networks
While extensive studies have been carried out in the past several years for many sensor applications, they cannot be applied to the network with extremely low and intermittent con...
Yu Wang, Hongyi Wu, Feng Lin, Nian-Feng Tzeng
FOCS
2005
IEEE
16 years 1 days ago
Truthful and Near-Optimal Mechanism Design via Linear Programming
We give a general technique to obtain approximation mechanisms that are truthful in expectation. We show that for packing domains, any α-approximation algorithm that also bounds ...
Ron Lavi, Chaitanya Swamy
ICCAD
1994
IEEE
131views Hardware» more  ICCAD 1994»
15 years 10 months ago
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
Hannah Honghua Yang, D. F. Wong