9477 search results - page 105 / 1896 » Design is as Easy as Optimization |
185
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IPPS
2006
IEEE
16 years 13 days ago
2006
IEEE
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
135
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ICCAD
2004
IEEE
16 years 3 months ago
2004
IEEE
In this paper, we have analyzed ond modeled the fiilure probabilities ofSRAM cells due to process parameter variations. A method to predict the yield of a memoiy chip based on the...
162
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JCP
2008
15 years 6 months ago
2008
-In this paper a nonlinear programming approach is used for the minimization of total communication cost to determine the optimum room dimensions for each room. The nonlinear progr...
195
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IPPS
2006
IEEE
16 years 13 days ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
171
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DAC
1996
ACM
15 years 10 months ago
1996
ACM
In this paper, we study the problem of decomposing gates in fanin-unbounded or K-bounded networks such that the K-input LUT mapping solutions computed by a depthoptimal mapper hav...