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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
16 years 3 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
ISPDC
2008
IEEE
16 years 25 days ago
Performance Analysis of Grid DAG Scheduling Algorithms using MONARC Simulation Tool
This paper presents a new approach for analyzing the performance of grid scheduling algorithms for tasks with dependencies. Finding the optimal procedures for DAG scheduling in Gr...
Florin Pop, Ciprian Dobre, Valentin Cristea
SIGIR
2009
ACM
16 years 29 days ago
Evaluating web search using task completion time
We consider experiments to measure the quality of a web search algorithm based on how much total time users take to complete assigned search tasks using that algorithm. We first ...
Ya Xu, David Mease
CANDC
2009
ACM
16 years 29 days ago
Visualization and empowerment
Data visualization, commonly used to make large sets of numerical data more legible, also has enormous potential as a storytelling tool to elicit insights on long-standing social ...
Indhira Rojas, Wendy Ju
CSCW
2010
ACM
16 years 3 months ago
Opening up the family archive
The Family Archive device is an interactive multi-touch tabletop technology with integrated capture facility for the archiving of sentimental artefacts and memorabilia. It was dev...
David S. Kirk, Shahram Izadi, Abigail Sellen, Stua...