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ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
16 years 14 days ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
IJMMS
2008
62views more  IJMMS 2008»
15 years 6 months ago
Iterative design of MOVE: A situationally appropriate vehicle navigation system
Drivers need assistance when navigating an unfamiliar route. In-vehicle navigation systems have improved in recent years due to the technology advances, but are sometimes problema...
Joonhwan Lee, Jodi Forlizzi, Scott E. Hudson
FCCM
1998
IEEE
99views VLSI» more  FCCM 1998»
15 years 10 months ago
FPGA-Based Architecture Evaluation of Cryptographic Coprocessors for Smartcards
In 1996, about 600 million IC-cards were manufactured worldwide. Due to very small die sizes (max. 25 mm2 ) smartcards encounter more severe restrictions than conventional coproces...
Hagen Ploog, Dirk Timmermann
ACISICIS
2010
IEEE
15 years 8 months ago
User-Model-Based Evaluation for Interactive Image Retrieval
Abstract--User-system interaction is sometimes a cumbersome element of non-textual information access. Image retrieval systems now incorporate various interaction mechanisms. Howev...
Masashi Inoue, Manh Hong Nguyen
DATE
2010
IEEE
163views Hardware» more  DATE 2010»
15 years 11 months ago
AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs
Aggressive technology scaling has an ever-increasing adverse impact on the lifetime reliability of microprocessors. This paper proposes a novel simulation framework for evaluating...
Lin Huang, Qiang Xu