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HPCA
2009
IEEE
16 years 7 months ago
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...
DCC
2002
IEEE
16 years 6 months ago
Optimized Edgebreaker Encoding for Large and Regular Triangle Meshes
We present a technique designed aiming to improve the compression of the Edgebreaker CLERS string for large and regular meshes, where regularity is understood as the compactness o...
Andrzej Szymczak
ICC
2007
IEEE
107views Communications» more  ICC 2007»
16 years 1 months ago
The SILO Architecture for Services Integration, controL, and Optimization for the Future Internet
— We propose a new internetworking architecture that represents a departure from current philosophy and practice, as a contribution to the ongoing debate regarding the future Int...
Rudra Dutta, George N. Rouskas, Ilia Baldine, Arno...
ATAL
2007
Springer
16 years 1 months ago
On Revenue-Optimal Dynamic Auctions for Bidders with Interdependent Values
In a dynamic market, being able to update one’s value based on information available to other bidders currently in the market can be critical to having profitable transactions. ...
Florin Constantin, David C. Parkes
IEEEPACT
2006
IEEE
16 years 28 days ago
Core architecture optimization for heterogeneous chip multiprocessors
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi