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FPGA
2008
ACM
184views FPGA» more  FPGA 2008»
15 years 8 months ago
Mapping for better than worst-case delays in LUT-based FPGA designs
Current advances in chip design and manufacturing have allowed IC manufacturing to approach the nanometer range. As the feature size scales down, greater variability is experience...
Kirill Minkovich, Jason Cong
TCAD
2008
118views more  TCAD 2008»
15 years 6 months ago
Variability-Aware Bulk-MOS Device Design
As CMOS technology is scaled down toward the nanoscale regime, drastically growing leakage currents and variations in device characteristics are becoming two important design chall...
Javid Jaffari, Mohab Anis
GECCO
2009
Springer
174views Optimization» more  GECCO 2009»
15 years 4 months ago
Shape grammars and grammatical evolution for evolutionary design
We describe the first steps in the adoption of Shape Grammars with Grammatical Evolution for application in Evolutionary Design. Combining the concepts of Shape Grammars and Genet...
Michael O'Neill, John Mark Swafford, James McDermo...
DAC
2008
ACM
16 years 7 months ago
Low power passive equalizer optimization using tritonic step response
A low power passive equalizer using RL terminator is proposed and optimized in this work. The equalizer includes an inductor in series with the resistive terminator, which boosts ...
Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch,...
DAC
2003
ACM
16 years 7 months ago
Scalable modeling and optimization of mode transitions based on decoupled power management architecture
To save energy, many power management policies rely on issuing mode-change commands to the components of the system. Efforts to date have focused on how these policies interact wi...
Dexin Li, Qiang Xie, Pai H. Chou