32117 search results - page 6218 / 6424 » Design for Unanticipated Use.. |
182
click to vote
IPPS
2006
IEEE
16 years 13 days ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
196
click to vote
IROS
2006
IEEE
16 years 13 days ago
2006
IEEE
– A sensor platform has been developed that is capable of both aerial and terrestrial locomotion, as well as transitioning between the two. The Morphing Micro Air-Land Vehicle (M...
160
click to vote
IROS
2006
IEEE
16 years 13 days ago
2006
IEEE
— Our long-term objective is to develop robots that engage in natural language-mediated cooperative tasks with humans. To support this goal, we are developing an amodal represent...
174
click to vote
ISCA
2006
IEEE
16 years 13 days ago
2006
IEEE
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
166
click to vote
MICRO
2006
IEEE
16 years 12 days ago
2006
IEEE
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...