We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
We demonstrate the H3Viewer graph drawing library, which can be run from a standalone program or in conjunction with other programs such as SGI's Site Manager application. Our...
Abstract — The principles employed in the development of modern RF simulators are introduced and the various techniques currently in use, or expected to be in use in the next few...
A packet scheduler in a quality-of-service QoS network should be sophisticated enough to support stringent QoS constraints at high loads, but it must also have a simple implemen...