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INFOCOM
2005
IEEE
16 years 11 days ago
Topology aware overlay networks
— Recently, overlay networks have emerged as a means to enhance end-to-end application performance and availability. Overlay networks attempt to leverage the inherent redundancy ...
Junghee Han, David Watson, Farnam Jahanian
IPPS
2005
IEEE
16 years 11 days ago
Fast Address Translation Techniques for Distributed Shared Memory Compilers
The Distributed Shared Memory (DSM) model is designed to leverage the ease of programming of the shared memory paradigm, while enabling the highperformance by expressing locality ...
François Cantonnet, Tarek A. El-Ghazawi, Pa...
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
16 years 11 days ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
181
Voted
ISPAN
2005
IEEE
16 years 11 days ago
Process Scheduling for the Parallel Desktop
Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power ma...
Eitan Frachtenberg
180
Voted
ISPASS
2005
IEEE
16 years 11 days ago
BioBench: A Benchmark Suite of Bioinformatics Applications
Recent advances in bioinformatics and the significant increase in computational power available to researchers have made it possible to make better use of the vast amounts of gene...
Kursad Albayraktaroglu, Aamer Jaleel, Xue Wu, Mano...
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