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    DAC
    1999
    ACM
    129views Computer Architecture» more  DAC 1999»
    Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction
    16 years 7 months ago
    Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction
    Download  computing.ece.vt.edu
    Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
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    ANSS
    2000
    IEEE
    94views Modeling and Simulation» more  ANSS 2000»
    Using the DEVS Paradigm to Implement a Simulated Processor
    15 years 11 months ago
    Using the DEVS Paradigm to Implement a Simulated Processor
    Download  www1.cs.columbia.edu
    This work is devoted to present the design and implementation of Alfa-1, a simulated computer with educational purposes. The DEVS formalism was used to attack the complexity of th...
    Sergio Daicz, Alejandro Troccoli, Sergio Zlotnik, ...
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    DT
    2007
    65views more  DT 2007»
    A Highly Scalable GALS Crossbar Using Token Ring Arbitration
    15 years 6 months ago
    A Highly Scalable GALS Crossbar Using Token Ring Arbitration
    Download  async.bu.edu
    - This paper presents a new low latency Crossbar design that can be used to interface systems working at different frequencies. For case of multiple input ports contending for same...
    Tejpal Singh, Alexander Taubin
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    ICETET
    2009
    IEEE
    131views Emerging Technology» more  ICETET 2009»
    Low Energy Tree Based Network on Chip Architectures Using Homogeneous Routers for Bandwidth and Latency Constrained Multimedia A
    16 years 1 months ago
    Low Energy Tree Based Network on Chip Architectures Using Homogeneous Routers for Bandwidth and Latency Constrained Multimedia A
    Download  www.cse.iitk.ac.in
    Abstract— Design of Network on chip architectures for multimedia applications is being widely studied. This involves design decisions at various levels of hierarchy. Topology des...
    Deepak Majeti, Aditya Pasalapudi, Kishore Yalamanc...
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    DAC
    2007
    ACM
    96views Computer Architecture» more  DAC 2007»
    Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits
    16 years 7 months ago
    Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits
    Download  www.eecg.toronto.edu
    Tomasz S. Czajkowski, Stephen Dean Brown
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