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JCP
2008
178views more  JCP 2008»
15 years 6 months ago
Building Design Optimization Using Sequential Linear Programming
-In this paper a nonlinear programming approach is used for the minimization of total communication cost to determine the optimum room dimensions for each room. The nonlinear progr...
Rekha Bhowmik
VLSID
2005
IEEE
124views VLSI» more  VLSID 2005»
15 years 12 months ago
Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder
In this paper, we have proposed a design technique for the reversible circuit of Binary Coded Decimal (BCD) adder. The proposed circuit has the ability to add two 4bits binary var...
Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury
GLVLSI
1999
IEEE
90views VLSI» more  GLVLSI 1999»
15 years 10 months ago
A Memory Design in QCAs using the SQUARES Formalism
We present a formalism for implementing circuits with Quantum-dot Cellular Automata (QCA), comprising a set of standard circuit elements with uniform layout rules. The formalism s...
Daniel Berzon, Terry J. Fountain
DAC
1994
ACM
15 years 10 months ago
Minimal Delay Interconnect Design Using Alphabetic Trees
Abstract - We propose a new algorithm for the performancedriven interconnect design problem, based on alphabetic trees. The interconnect topology is determined in a global manner a...
Ashok Vittal, Malgorzata Marek-Sadowska
ISLPED
1995
ACM
113views Hardware» more  ISLPED 1995»
15 years 10 months ago
Low delay-power product CMOS design using one-hot residue coding
: CMOS implementations of arithmetic units for One-Hot Residue encoded operands are presented. They are shown to reduce the delay-power product of conventional, fully-encoded desig...
William A. Chren Jr.