788 search results - page 58 / 158 » Design and use of a system-level specification and verificat... |
206
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TCAD
2008
15 years 6 months ago
2008
Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timin...
194
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JSW
2006
15 years 6 months ago
2006
Abstract-- Leveraging service oriented programming paradigm would significantly affect the way people build software systems. However, to achieve this goal a solid software design ...
157
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FMCAD
2008
Springer
15 years 7 months ago
2008
Springer
Performing synthesis and verification in isolation has two undesirable consequences: (1) verification runs the risk of becoming intractable, and (2) strong sequential optimization...
199
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ECBS
2007
IEEE
15 years 10 months ago
2007
IEEE
We present in this paper a new approach for the automatic verification and performance analysis of SysML activity diagrams. Since timeliness is important in the design and analysi...
171
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EUROMICRO
1996
IEEE
15 years 10 months ago
1996
IEEE
Transformational design integrates design and verification. It combines "correctness by construciion" and design creativity by the use ofpre-proven behaviour preserving ...