788 search results - page 45 / 158 » Design and use of a system-level specification and verificat... |
172
click to vote
DSD
2004
IEEE
15 years 10 months ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
148
click to vote
ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
The use of CMOS nanometer technologies at 65 nm and below will pose serious challenges on the design of mixed-signal integrated systems in the very near future. Rising design comp...
161
click to vote
DAC
1996
ACM
15 years 10 months ago
1996
ACM
A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced nois...
166
click to vote
ITC
2003
IEEE
15 years 11 months ago
2003
IEEE
Functional verification of complex designs largely relies on the use of simulation in conjunction high-level verification languages (HVL) and test-bench automation (TBA) tools. In...
115
click to vote
ICCAD
2002
IEEE
16 years 3 months ago
2002
IEEE
The challenges for developing an ESD (Electro-static Discharge) layout extractor originate from unconventional layout patterns of ESD protection devices, parasitic ESD device extr...