Sciweavers

788 search results - page 44 / 158
» Design and use of a system-level specification and verificat...
Sort
View
DATE
2009
IEEE
126views Hardware» more  DATE 2009»
16 years 1 months ago
Fast and accurate protocol specific bus modeling using TLM 2.0
—The need to have Transaction Level models early in the design cycle is becoming more and more important to shorten the development times of complex Systems-on-Chip (SoC). These ...
H. W. M. van Moll, Henk Corporaal, Víctor R...
DGO
2004
108views Education» more  DGO 2004»
15 years 7 months ago
A Project to Assess Voting Technology and Ballot Design
The interdisciplinary project uses a variety of research designs, data collection methodologies, and analysis techniques and two ballot designs to assess five commercially availab...
Paul S. Herrnson, Richard G. Niemi, Benjamin B. Be...
ICCAD
2005
IEEE
100views Hardware» more  ICCAD 2005»
16 years 3 months ago
Performance-centering optimization for system-level analog design exploration
In this paper we propose a novel analog design optimization methodology to address two key aspects of top-down system-level design: (1) how to optimally compare and select analog ...
Xin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih C...
JSA
2008
131views more  JSA 2008»
15 years 5 months ago
Formal verification of ASMs using MDGs
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...
Amjad Gawanmeh, Sofiène Tahar, Kirsten Wint...
DAC
1996
ACM
15 years 10 months ago
RTL Emulation: The Next Leap in System Verification
ion. Production use of text-based methodology has enabled designers to capture designs of hundreds of thousands of gates using graphic ESDA tools. Source: Data Quest (Verilog/VHDL ...
Sanjay Sawant, Paul Giordano